Manufacturers of consumer electronics are developing great devices with new features at an alarming rate.  Unfortunately, advances in battery technology are struggling to keep up with these new power hungry gadgets.  Streaming video, 3d graphics, and wireless data connections can all drain a device’s battery in a few short hours.  Some electrical engineers are taking action, and are trying new methods of power optimization at the chip level; one of their new tools is network theory.

A number of researchers are looking at applying principles of game theory to designing VLSI chips (very large scale integration –complex processors, etc).  Specifically, when devices get that small, signal noise becomes a major issue due to the close proximity of transistors.  Engineers have started modeling the networks of these circuits as games, trying to find the balance between logic gate size and signal noise, or propagation delay and interconnect placing, with a Nash equilibrium.  This way, less power can be lost to noise in this new, optimal flow pattern.  Some links to research in this field can be found here:

Simultaneous Interconnect Delay and Crosstalk Noise Optimization through Gate Sizing Using Game Theory

Game Theory and its Application to VLSI Physical Design

Similar research is being done at Rice University.  In a recent spotlight article in the Technology Review, Prof Krishna Palem talks about his Probabilistic CMOS.  Using a few ideas not yet covered in class, specifically Bayes rule, he is able to take advantage of conditional probabilities and have his circuits care less about values of lesser importance.   In these less important parts of the chip, the voltage is lowered, and while this increases the likelihood of error due to signal noise, the value coming from the calculation has already been deemed trivial.   Palem believes that these chips may account for a 10x increase in the battery life of many user devices. 

Probabilistic Chips